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Cmos Lna Design Techniques

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IEEE 2006 Custom Intergrated Circuits Conference (CICC) X/Ku Band CMOS LNA Design Techniques Bagher Afshar, Ali M. Niknejad Berkeley Wireless Research Center, Dept. of EECS, UC Berkeley, Berkeley, CA 94704, USA Abstract— This paper reports two 11 GHz low-noise ampli? ers (LNA) in 0. 18µm CMOS technology. A cascade two stage LNA achieves 12 dB of power gain, 3. 5 dB of noise ? gure, and an input/output match of ? 15 dB/? 27 dB at 11GHz, while consuming 28mA from 1. 8V supply. The second LNA is a modi? ed cascode ampli? er and it achieves 8 dB of gain, 3.

dB of noise ? gure, and an input/output match of ? 12 dB/? 15 dB at 11GHz, consuming 18mA from the 1. 8V supply. The paper also discusses design considerations such the effects of layout on frequency tuning and noise. iout Vbias Lg Vin Rs Ls M1 Rs Vin M2 Lg gmVgs i2ng gg Cgs Vgs iout i2nd Ls I. I NTRODUCTION Rapid evolution of wireless communication has resulted in a continuous trend towards utilizing higher frequencies for wideband communication applications.

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CMOS technology is of major interest for its low cost and high level of integration.

While much research has been done on integrating cellular and WLAN transceivers in CMOS and SiGe technology [1], very little work has been done at 10GHz (X-band, Ku-band). There are many interesting and important commercial applications in this frequency band, such as the satellite communication receivers for entertainment and high speed internet access. Current microwave receivers at this frequency are not only physically large, but are also expensive. Realization of such devices in standard CMOS will enable wider commercial adoption. On the other hand much research activity has recently focused on higher frequencies, such as he 60GHz band [2] and the 77GHz band [3]. Unfortunately microwave transmission-line based design techniques do not scale to relatively lower frequencies like 10GHz. Due to area constrains, circuits at these frequencies must employ relatively small lumped passive components, such as inductors ? 250pH , and such small reactances must be realized on-chip. As we shall see, realization of such inductors is challenging due to parasitic inductance of the layout. II. D ESIGN FOR L OW N OISE A simpli? ed small signal model for a simpli? ed inductive degenerated cascode LNA is shown in Fig. 1. Ignoring Cgd , the input impedance Zin is given by Zin ? gm Ls 1 + s(Ls + Lg ) + + rLg sCgs Cgs (1) Fig. 1. (a) Simpli? ed cascode LNA. (b) Small-signal model of (a) (M2 is ignored for simplicity). Which can be simpli? ed to [4] rLg + rt g mM 2 F ? 1+ + ?? gmM 1 Rs 1 + = Rs 10gmM 1 f fT 2 (3) ? g L ·? where ? = ? gd0 , ? = 1 + gmb , rLg = QgL , RL is the gm m g load resistance and rt = rg + rs + ri accounts for total gate resistance including induced gate noise. At a given frequency, given lossless feedback and matching networks, selection of the optimum device width and optimum bias voltage at each frequency results in an input match and an overall noise ? ure of Fmin , the minimum noise ? gure of the circuit [5]. Unfortunately, practical inductors have ? nite quality factor, requiring a careful trade-off between the input match and the noise ? gure. III. LNA C IRCUIT D ESIGN The simpli? ed schematics of the single-stage cascode and two-stage cascade LNA’s are shown in Fig. 2 and Fig. 3. Both topologies utilize inductive degeneration for input matching to 50?. Degeneration also improves the linearity by forming a negative series-series feedback. For the cascade two-stage design, the second stage also employs inductive degeneration to improve the linearity of the ampli? r (rather than for matching). In Fig. 3, the output of ? rst stage will resonate with the total capacitance connected to the drain of M3 . The advantage of using a single transistor for the ? rst stage is to lower the overall noise contribution of the input stage. In single-stage LNA of Fig. 2, the impedance seen through the drain of M1 without considering Lr and Cr could be modeled by Rp in parallel with Cp , as shown in Fig. 4. At high frequencies, the parasitic capacitance at the drain node of M1 signi? cantly reduces the overall impedance to ground and thus raises the noise contribution from cascode transistor

By de? nition, the noise factor F is given by the total output noise normalized by the noise at the output arising only from the source, or ? F = i2 R + i2 r o| o| s g +rs +ri + i2 o| Id2 M1 + i2 o| Id2 M2 + i2 R o| L i2 R o| s (2) 1-4244-0076-7/06/$20. 00 ©2006 IEEE P-47-1 389 Vdd Vdd Vdd Vdd Vdd R2 M2 Ld C3 Ld1 Ld2 R5 C6 C5 M5 C4 Vout Vout C2 Cr Vin C1 Lg M3 Rs R3 Vin C1 Lg M1 Lr R1 Ls M4 Ls2 Rs Ls1 R4 Bias1 Bias1 Bias2 Fig. 2. Single-stage cascode LNA schematic. Fig. 3. Two-stage cascade LNA schematic. Vdd 2 vnM 2 + i2 n M2 Vdd Ld Vout i2 M 2 ? = o| ( gm2 + 1 gm2 Rp C1 s )2 p Rd (4) Iin M2 Vin Rp Zp Cp where i2 M 2 is output current noise due to transistor M2 . o| To improve the noise performance of the cascode design, the parasitic capacitance at the drain of M1 is resonated out by adding an inductor to the source of casode. This improves the noise performance of the cascode considerably, as shown in Fig. 2. This inductor should be sized carefully in order to resonate the unwanted capacitances at the desired frequency of operation. The size of the transistors are optimized for noise minimization at 11 GHz. To lower the noise ? ure, the transistors are biased very close to maximum fT of process. The peak fT of 52GHz is achieved at a certain gate bias voltage. At higher gate bias voltage, the fT drops due to high ? eld mobility degradation. For power ef? ciency, the transistor should be biased slightly before reaching this optimum fT point. By backing off slightly from this point, the noise degradation is small but power saving is large. Because the optimum noise resistance is not equal to 50? , the transistors are not matched exactly, but rather the matching is traded off for low noise ? ure. Due to the high frequency of operation, the degeneration inductance, used for matching is very small and this necessitates careful consideration of the loop return currents in the layout. IV. L AYOUT AND S TABILITY I SSUES A. LNA Layout Consideration In high frequency circuits, the most important effects tend to be the most dif? cult to simulate. For calculating the effective reactance of spiral inductors, we must consider the contribution of routing and ground/supply inductance. For instance, in the input matching network shown in Fig. , the inductance from the source node of M1 to the input voltage ground terminal contributes to the inductive degeneration. To capture this extra inductance, we must also include the effects of the currents ? owing on the ground plane return path. A custom Fig. 4. Input impedance seen at the gate of the cascode transistor. simulation tool ASITIC [6] was used to estimate these parasitic effects. The layout of the transistors were optimized to achieve low noise at high frequency. To minimize the impact of transistor substrate resistance, a ringed substrate contact structure was placed as close as possible to the transistors. A multi-? ger transistor layout is employed to decrease the gate resistance. This translates to higher fmax and lower device noise. Even though a double-gate contact lowers the gate resistance even further, this was not employed in this design. B. LNA Stability Consideration Stability is an important consideration in the design of ampli? ers, especially at higher frequencies. One important node prone to oscillation at high frequencies is the gate of the cascode transistor. Since the input impedance of a capacitively degenerated device has a negative real part, a high Q parasitic inductance at the gate of cascode can form a Colpitts oscillator.

If we ignore Cgd , the input resistance in Fig. 4 is given by Zin = 1 1 + Zp (1 + gm ) sCgs sCgs (5) The real part is given by Rin ? = 2 gm Rp Cp ? 2 Cgs Rp ? 2+1 (Rp Cp ? ) (Rp Cp Cgs ? 2 )2 + (Cgs ? )2 (6) P-47-2 390 Gnd Vdd Vbias Gnd Vdd Gnd Gnd Gnd RFin RFout RFin RFout Gnd Gnd Gnd Gnd Gnd Gnd Bias1 Fig. 5. Bias2 Fig. 6. Die photo of the two-stage LNA test chip. Die photo of the single-stage LNA test chip. where we have used Zp = Rp Rp Cp s + 1 0 (7) -5 -10 S11 [dB] -15 Single-stage LNA (meas) Single-stage LNA (sim) To improve the stability of the cascode ampli? er, a resistor was added to the gate of cascode to de-Q the resonator.

In this design, we estimated conservatively a parasitic gate inductance of 150 pH. A stabilizing resistor of value Rex = 10? was added to the gate of the cascode transistor of LNA. The value of this resistor cannot be chosen arbitrarily large, as it degrades the noise ? gure and reduces the ef? cacy of the bypass capacitor. V. M EASUREMENT R ESULTS The two prototype LNAs were fabricated and measured. As shown in Fig. 2 and Fig. 3, the outputs are matched directly to 50?. Capacitors are implemented by Metal-Insulator-Metal (MIM) capacitors that provide good linearity and small parasitic capacitance. C2 ?

C5 are output matching capacitors, R2 and R5 are stabilizing resistors and Cr is a coupling capacitor for separating the series resonant tank at the source of M2 at DC. The gates of the two-stage LNA are biased at 0. 9V and the gate of single-stage LNA at 1. 05V. The optimum width is selected ( 57? 2µ ), which is approximately the same 180n for all the transistors. The inductor values for the two-stage LNA range from 300pH – 900pH. For the cascode LNA the inductor values range from 250pH – 1. 11nH. The test chips are fabricated using a 0. 18µm CMOS technology. The die photos are shown in Fig. 5-6. The single-stage LNA occupies an area of 0. 6 ? 0. 58 mm2 and the two-stage LNA occupies an area of 0. 66 ? 0. 72 mm2 (including pads). The simulated and measured S-parameter data are shown in Fig. 7-9. The experimental results show that single-stage LNA has a peak gain of 8 dB at 11GHz, and the two-stage LNA a peak gain of 12 dB also at 11GHz. As expected, the S12 of two-stage LNA is more than 10 dB better than single-stage LNA. Two-stage LNA (sim) -20 -25 Two-stage LNA (meas) -30 8 9 10 11 12 Frequency [GHz] 13 14 Fig. 7. Measured and simulated input match (s11 ). 16 Two-stage S21(sim) 14 12 S21[dB] 10 8 6 4 2 0 8 9 Single-stage S21(meas) Single-stage S21(sim) Two-stage S21(meas) 0 11 12 Frequency[GHz] 13 14 Fig. 8. Measured and simulated voltage gain (s21 ). P-47-3 391 0 -5 -10 -15 S12,S22 [dB] -20 -25 -30 -35 -40 -45 -50 8 9 10 11 12 Frequency [GHz] 13 14 Two-stage S12(meas) Two-stage S22 (meas) Single-stage S12(meas) Single-stage S22 (meas) Fig. 9. Measured output match and isolation (s22 ,s12 ). 5 Single-stage (sim) Two-stage (meas) 4 Single-stage (meas) 3. 5 4. 5 Noise Figure [dB] In Fig. 10 we plot the noise ? gure data of the two LNAs. Cable losses have been measured separately and de-embedded from the data. The minimum noise ?gure for both designs happen at around 10 ? 1GHz, at 3 dB for the single-stage design, and 3. 3 dB for the two-stage LNA. Careful layout and passive modeling resulted in fairly close agreement between simulations and measurements, especially with regards to the center frequency. The absolute value of gain, though, is lower by about 3 dB compared to simulation. The pad loss or inaccurate transistor models could account for the difference, and the source of this error is currently under investigation. Model inaccuracy could also be accounted for difference between measured and simulated noise ? gure. The measured noise ? gure of the two-stage LNA is about 0. dB higher than the other design. The decrease in gain of the ? rst stage in the two-stage LNA design could increase the noise contribution of the second stage and increase the overall noise ? gure. A two-tone test for third-order intermodulation distortion is performed for the two LNAs with two signals around 11GHz separated by 10MHz from each other and is shown in Fig. 11. The IIP3 is +5 dBm and +10 dBm and the input 1-dB compression point is measured at ? 8. 5 dBm and ? 2. 25 dBm for two-stage and single-stage LNA respectively. The singlestage LNA has better IIP3 compared to two-stage design.

The linearity of the LNA is important in sub-1dB low noise applications where the CMOS LNA will be preceded by an ultra-low noise preampli? er. VI. C ONCLUSION Two different topologies for a X/Ku band CMOS LNA have been tested and compared. A series resonant tank was added to the source of cascode transistor in single-stage LNA to improve noise ? gure at high frequencies. The effects of layout on frequency tuning, noise, and stability have been addressed in the design. ACKNOWLEDGMENT The authors would like to thank Conexant Systems for their support of this research project. The authors also thank BWRC industrial members.

In particular, the authors acknowledge the help of Zhiming Deng, Nuntachai Poobuapheun, Ehsan Adabi and Mounir Bohsali. R EFERENCES [1] J. R. Long, “A low-voltage 5. 1-5. 8GHz image-reject downconverter RFIC,” IEEE J. Solid-State Circuits,vol. 35, pp. 1320-1328, Sept. 2000. [2] C. H. Doan, S. Emami, A. M. Niknejad, and R. W. Brodersen, “Millimeter-wave CMOS design,” IEEE J. Solid-State Circuits, vol. 40, pp. 144-155, Jan. 2005. [3] A. Babakhani, X. Guan, A. Komijani,A Natarajan, A. Hajimiri, “A 77GHz 4-Element Phase-Array Reciever with On-Chip Dipole Antennas in Silicon,” IEEE ISSCC Dig. Tech. Papers, pp. 180-181, Feb. 006. [4] S. S. Taylor, “FET Noise Modeling and LNA Design,” talk at UC Berkeley, April 2004. [5] D. K. Shaeffer, et al. , “A 1. 5-V, 1. 5-GHz CMOS low noise ampli? er,” IEEE J. Solid-State Circuits, vol. 32, pp. 745-759, May 1997. [6] A. M. Niknejad, “Modeling of passive elements with ASITIC,” RFIC Digest of Papers, 2002, pp. 303-306. 3 Two-stage (sim) 2. 5 8 9 10 11 12 Frequency[GHz] 13 14 Fig. 10. Measured and simulated noise ? gure. 40 20 Pout [dBm] 0 -20 -40 -60 -80 30 Single-stage IIP3 (meas)= +10dBm Two-stage IIp3 (meas)= +5dBm 25 20 15 10 5 Pin [dBm] 0 5 10 15 Fig. 11. Measured IIP3 at 11GHz. P-47-4 392

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Cmos Lna Design Techniques. (2018, Jan 28). Retrieved from https://graduateway.com/cmos-lna-design-techniques/

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