A traditional die is a little polyhedral object, normally cubic in form. It generates a random figure in the scope of one to six. There are besides non – cubelike die with different figure of faces such as tetrahedrons ( four faces ) , octahedrons ( eight faces ) or dodecahedrons ( twelve faces ) . A digital die is an alternate device that can be used to replace the traditional device with the aid of a numeral show. It is controlled with the aid of a switch. The count will expose Numberss indiscriminately from one to six on the 7 section show in a push of the button.
1.1 Rules of the Game:
The Digital Dice game consists of two participants, Player A and Player B.
Both the participants, Player A and Player B, are given a switch each to command the dies.
In this game, merely one participant is allowed to play at a clip and the input of merely one participant is counted at a clip. A LED indicates the participant ‘s bend.
The end product of each participant ‘s throw is added to the end product of their old throw ‘s figure. This gives their concluding mark.
The maximal count is taken as 30. When any one of the participants reaches the maximal count of 30, the Game ends. The participant ( Player A or Player B ) has won the game.
The pager along with a light indicates the participant ‘s triumph.
This chapter gives a elaborate description of the block diagram for the Digital Dice game undertaking. It discusses the chief parts and besides gives a elaborate account on the same.
2.1 Block Diagram
The chief parts of the block diagram as shown in figure 1 are:
1. 2 – Clock pulsations
2. Random Number Generator
3. Digital Dice Display
3. 2 Adder Circuits ( including the seven – section FND show )
4. ‘Game – Over ‘disabling circuit
5. Reset switch
Fig 1: Block Diagram for the digital die game
2.2 Clock Pulse
Clock pulsation is a signal used to synchronise the operations of an electronic system. They are uninterrupted and exactly spaced alterations in electromotive force. The chief purpose of this portion in the circuit is to give the appropriate clock pulsations to the following circuits to do a advancement in the game.
For this intent, 2 redstem storksbills have been employed for each participant. Here a particular circuit has to be employed so as non to let the participant that has already played to play until his opposition has had his opportunity. This is done by utilizing the Toggling characteristic of J-K reversal ( IC 7476 ) . Each of the 2 clock pulsations is so ANDED with the 2 end products of J-K reversal which is Q and Q ‘ . At any point of clip, merely one of Q and Q ‘ will be HIGH and so merely one participant will be able to play at a clip as per the regulations of the game. The clock of the other participant being ANDED with zero will be uneffective. The appropriate clock so will go through through the OR gate and into the input clock of the J-K reversal, therefore toggling it and supplying a opportunity for the other participant to play. The end product of the OR gate is given to the remainder of the full circuit as a ‘common clock ‘ .
2.3 Random Number Generator
The chief purpose of this portion is to bring forth any figure between 1 and 6 ( inclusive ) i.e. 3-bit binary figure, similar to a three-dimensional die where each face represents a figure. However, the figure generated in this circuit is non in any sort of a predictable sequence and is in a absolutely random similar to an existent die in such a game.
This is facilitated by the usage of IC NE-555, which generates series of end product clock pulsations. The resistances and capacitances environing it explicate a peculiar RC clip changeless and the IC so continues to bring forth end product clock pulsations till the terminal of this clip period. So, when the appropriate clock pulsation is obtained from the above discussed clock pulsation circuit, the pulsations generated by IC NE-555 are fed to the following Integrated Circuit, Binary Ripple Counter ( IC – 7493 ) . Another Integrated Circuit, Decade Counter ( IC – 7490 ) can besides be used. The Binary Ripple Counter counts from 0 to 5 i.e. 3-bit Numberss provided the MSB ( Most important Bit ) of the counter is non considered. After the count reaches five, the Counter resets to nothing. When many clock pulsations are received by it in a individual time-constant period, it counts from 0-5 many times and outputs any of these Numberss. This is known as Random Number Generation.
However, the Numberss obtained from the above process are between 0 and 5 ( inclusive ) and the coveted Numberss are from 1 – 6. This is taken into history by including another Integrated circuit, Binary Parallel Adder ( IC – 7483 ) which increments the above generated figure by 1 as it is between 0 and 5. The end product of the Binary Parallel Adder is the concluding coveted random figure which is so fed into the Digital Dice-Display circuit as shown in the figure 1.
2.4 Digital Dice Display Circuit
The lone intent of this portion is to demo the face of the Dice corresponding to the figure generated by the randomizer circuit.
This is done with the aid of a BCD – 7 Segment decipherer which is used to drive a common anode 7 section show. The end product of the above discussed circuit forms the input for the BCD which so enters the input of seven – section decipherer. The random figure generated by the random figure generator circuit will be displayed on the 7 – section show when the button is pushed by a participant. The figure displayed is any figure between 1to 6 in a complete random sequence.
2.5 Adder Circuits
This is the core portion of this game. All the Numberss generated so far should be accounted for each participant independently in the signifier of their mark. As discussed before, this mark gets incremented by each surrogate autumn of Numberss on the die. The Adder circuit performs this map.
The Adder circuit is made up of a group of 3 AND Gatess. One of the inputs of the AND gates is a spot of the random figure coevals and the other input is one of Q and Q ‘ ( end products of the J – K flip-flop as discussed above in the ‘Clock Pulses ‘ subdivision ) . Hence, at a clip, the mark of merely the appropriate participant gets incremented by the figure on the die. Whereas the mark of the other participant remains the same ( i.e. gets added by 0 ) .
The end products of the 3 AND Gatess enter the Integrated Circuit, Binary Parallel Adder ( IC – 7483 ) as inputs for A. The Most important spot ( MSB ) A is kept grounded. The inputs for B come from the end product of the Integrated circuit, 4-bit Register ( IC – 74194 ) and these shops the Least important spot ( LSB ) of the concluding mark. There are two Binary Parallel Adders and the end product of this 1st Adder ( IC – 7483 ) is connected to the 2nd Adder ( IC – 7483 ) , which converts the added binary figure into its denary equivalent and shops the end product in the above mentioned 4 – Bit registry ( IC – 74194 ) . This transition is produced with the aid of different logic Gatess ( AND and OR Gatess ) . When the binary figure is greater than 9, 6 ( 0110 ) is added to it, else 0 ( 0000 ) is added to the figure therefore bring forthing the tantamount LSB denary figure. Therefore, the LSB remains less than or equal to 9, therefore stand foring the mark in denary signifier.
The same technique is applied to the Most Significant Bit of the mark. Here, 1 is added to the MSB of the Binary Parallel Adder ( IC – 7483 ) , if the above generated binary figure is greater than 9. The other input for this 3rd IC-7483 comes from another 4-bit registry ( IC – 74194 ) . Therefore, the MSB can besides demo denary Numberss from 0 – 9.
The same Most Significant Bit and Least Significant Bit Numberss from the Adders are given as input to Integrated circuit, BCD ( IC – 7447 ) , which is the driver IC to the Seven-Segment LED show. The end products of this Integrated circuit are fed into the LT-543, to demo the corresponding Numberss.
An of import point to be noted here is that the same ‘common clock ‘ is given to the above mentioned IC-74194 registries so that they can end product the stored Numberss each clip.
2.6 ‘Game – Over ‘ Disabling Circuit
This portion of the block diagram indicates the End of the game, i.e. Game – Over. The game is considered to be over one time the mark of any one of the two participants ( Player A or Player B ) reaches/crosses the mark of 30.
The 2nd input of the Most Significant Spots of the Most Significant Bit of the denary mark of both the participants form the input to the NOR gate. Therefore, when any mark reaches/crosses 30, the 2nd Most Significant Bit becomes HIGH. Therefore NOR end product becomes LOW ( i.e. In a NOR gate, when any one of the inputs is HIGH, the end product is LOW ) . This is so ANDED with the clock-pulse to be given to the J-K reversal. As a consequence, the J-K reversal does non have any clock. Therefore, the ‘toggling ‘ characteristic of the somersault – floating-point operation Michigans. Therefore, the random figure coevals Michigans and the Dice-display remain unchanged. And, eventually the tonss remain fixed. Therefore, the game has come to an terminal
The winning participant ( Player A or Player B ) is identified by the tone of the buzzer/alarm along with a LED to supply an indicating visible radiation. This is holding one terminal on the above 2nd Most Significant Bit and the other terminal grounded.
2.7 Reset Switch
This is besides a really of import portion of the game. The map of this switch is to convey the game back to get down from any point of clip.
This is performed with the aid of a Combinational Circuit and a ‘Push-to-OFF ‘ switch. This is a sort of switch which has its 2 terminals ever connected, except when pressed/pushed. Therefore, one terminal of the switch is grounded. Therefore, by default this makes the clear inputs of all registries HIGH. Here, the registries employ Active Low Clear inputs.
When the switch is non pushed, HIGH clear is fed to the registries via a NOT gate. Therefore, normal operation of all the registries is obtained. Besides, the end product drawn from the OR gate so depends on the end product from the AND gate ( the 2 inputs of the AND gate semen from the 2nd Most Significant Bit and 3rd Most Significant Bit of the end product of the Binary Ripple Counter, IC – 7493 ) .
When the switch is pressed, the connexion of its 2 terminals gets broken and therefore doing the Clear input to all registries LOW via the NOT gate ( i.e. all registries are cleared ) . Therefore, one of the inputs to the IC – 7483 Adders become 0000. And, besides the input of the OR gate becomes HIGH, thereby disregarding the 2nd input and therefore supplying HIGH end product to the RO ( 1 ) Clear input of the Binary rippling counter, IC – 7493. Now, the counter is reset by 2nd Clear input RO ( 2 ) as it becomes HIGH, supplying 0000 end product. This forms the other input of Binary analogue adder, IC – 7483. Therefore, the Adder circuits display 00 in the 7 – section show. This 0000 end product is so carried via the Binary analogue adder, IC – 7483 ( here the input carry is besides 0 ) to the Dice-display circuit which displays 00.
Random Number Generation Circuit
This chapter explains the circuit diagram required for the random figure coevals and the digital – die show. It besides talks about the working for the same.
3.1 Circuit Diagram
The below figure ( figure 2 ) shows the circuit diagram used for the random figure coevals of a digital die.
Fig 2: Random Number Generation Circuit
Figure 2 shows the circuit diagram to bring forth any random figure between 1 and 6 and expose it on the 7 – section show. In operation, a clock frequence of 50 Hz is generated by the pulse generator. It is ANDED with the push button. When the push button is pressed, the clock pulsation generates a series of clock pulsations. The combination of the clock pulsation and the push button forms the counter clock for the Binary Ripple Counter ( IC – 7493 ) . This counter behaves as a Mod – 6 Counter and it counts from 0 – 5. Once the count reaches 5, it resets to zero. Therefore, the connexion of QB ( with value 2 ) to R0 ( 1 ) and QC ( with value 4 ) to R0 ( 2 ) severally.
The end product of this counter is connected to the input A of the Binary Parallel Adder ( IC – 7483 ) , i.e. QA, QB, QC, QD to A1, A2, A3, A4 severally. The map of the adder is to add the figure 1 ( Binary 0001 ) to the end product from the Binary rippling counter. This is done by anchoring the pins B1, B2, B3 and the pin B4 is connected to the supply to acquire a value of 1.
The end product of the Adder is connected to the BCD – 7 section show, i.e. the pins 9, 6, 12, 15 are connected to pins 7, 1, 2, 6 severally. Therefore, any figure between 1 and 6 is displayed in a wholly random mode in the signifier of its denary equivalent on the 7 – section show.
This completes the random figure coevals and the Digital – die show parts of the block diagram.
3.3 Components Assembled
The undermentioned constituents have been assembled on a Bread Board in order to make a random figure show between 1 and 6.
A counter is a device which shops the figure of times a peculiar event or procedure has occurred, normally in connexion with a clock signal. Every counter requires a ‘square moving ridge ‘ clock signal to do them count. A square moving ridge clock signal ( as shown in figure 3 ) is a digital wave form with crisp passages between low ( 0V ) and high ( +Vs ) electromotive force, such as the end product from a 555 astable timer. Here it comes from the pulse generator.
Fig 3: A square moving ridge clock signal
Examples of numbering are digital redstem storksbills, tickers, timers found in a scope of contraptions from microwave ovens to VCRs and counters are besides found in everything from cars to prove equipments.
There are chiefly two types of counters:
In a rippling counter, there are a concatenation of reversals with the end product of each somersault – floating-point operation organizing the input for the following. Every clip the input of the somersault – floating-point operation alterations from high to low ( on the falling border ) , the province of the somersault floating-point operation end product alterations.
Ripple counters largely count on the falling-edge which is the high to low passage of the clock signal. They use this border as associating counters becomes easier as the most important spot ( MSB ) of one counter can drive the clock input of the following. This whole procedure occurs because the following spot must alter province when the old spot alterations from high to low – the point at which a carry must happen to the following spot.
Fig 4: Falling Edge clock input
The disadvantages of this counter are:
There is a little hold ( known as a Ripple Delay ) as the consequence of the clock ‘ripples ‘ through the concatenation of flip-flops. But in many circuits, this is non a job as it is far excessively short to be seen on a show.
In a logic system, the connexion to the rippling counter end products will do false counts which may bring forth ‘glitches ‘ in the logic system and thereby interrupt its operation. For illustration, a ripple counter altering from 0111 ( 7 ) to 1000 ( 8 ) will briefly demo 0110 ( 6 ) , 0100 ( 4 ) and 0000 ( 0 ) before 1000.
A synchronal counter has a more complex internal construction as compared to a ripple counter. The advantage of this counter over the ripple counter is that it ensures that all its end products change exactly together on each clock pulsation, thereby avoiding the brief false counts which occur with rippling counters.
Most synchronal counters count on the rising-edge ( mention figure 5 ) which is the low to high passage of the clock signal. They normally have carry out and transport in pins for associating counters without presenting any ripple holds.
Fig 5: Rising – border clock inputs
These counters have a synchronal reset which occurs on the following clock pulsation instead than instantly as in a ripple counter. Since reset must be performed on the maximal count required, it is a really of import map.
220.127.116.11 Binary Ripple Counter ( IC – 7493 )
This is the counter used in the circuit. Figure 3 shows a clock signal driving a 4-bit ( 0-15 ) counter. It is connected with LEDs ( Light Emitting Diodes ) to demo the province of the clock and counter end products QA – QD. And Q indicates the end product.
Fig 6: A 4 – Bit antagonistic and Clock input
A counter can be used to cut down the frequence of an input signal and therefore behaves as a frequence division counter ( as shown in figure 7 ) , i.e. they can be used to cut down the frequence of an input ( clock ) signal. Each phase of a counter halves the frequence, so here the LED on the first end product QA flashes at half the frequence of the clock LED, i.e. QA is 1/2, QB flashes at 1/4, QC at 1/8 and QD at 1/16 of the clock frequence. It is normally labeled as Q1, Q2 and so on. Qn is the n-th phase of the counter, stand foring 2n.
Fig 7: Frequency Division Process
Division by Numberss that are non powers of 2 is possible by resetting counters. Counters can be reset to zero before their maximal count by linking one ( or more ) of their end products to their reset input. The counter is in two subdivisions: Clock A for QA and Clock B for QB, QC and QD.
If the reset input is ‘active-low ‘ a NOT or NAND gate will be required to bring forth a low end product at the coveted count. ‘Active – low ‘ is indicated by a line drawn above reset. For illustration: ( state ‘reset-bar ‘ ) . The reset map requires an immediate reset on the following count.
18.104.22.168 Decade Counter ( IC – 7490 ) :
A decennary counter ( mention figure 8 ) is a binary counter that is designed to number to 10 or 1010 in binary, i.e. it counts the figure of pulsations geting at its input. The figure of pulsations is counted up till 9 and it appears in binary signifier on four pins of the IC. When the ten percent pulse arrives at the input, the binary end product is reset to zero ( 0000 ) and a individual pulsation appears at another end product pin.
This map is performed due to the fact that the NAND end product goes low, and resets the counter to zero. D traveling low can be a CARRY OUT signal, bespeaking that there has been a count of 10. So for 10 pulsations in the input, there is one pulsation end product. Therefore, the 7490 Decade Counter divides the frequence of the input by 10. And, if this pulsation is applied to the input of a 2nd 7490 decennary counter, so the 2nd IC will number the pulsations from the first IC i.e. for 100 pulsations input, there will be one pulse end product.
Fig 8: A Decade Counter
3.3.2 Binary Parallel Adder ( IC – 7483 )
The parallel adder precedes the binary counter, i.e. once the counter begins its count from 0 – 5, it so enters the adder where the binary 0001 is added to it.
The cardinal computational component in any circuit is the adder. The map of the parallel adder is to add two n – spot Numberss together. For this intent, n full – adders should be cascaded with each full – adder stand foring a column in the long add-on. The carry signals ‘ripple ‘ through the adder from right to go forth.
Figure 9 indicates the working of a logic full adder/ subtractor. The adder circuit has a manner control signal M which determines whether the circuit has to run as an adder or a subtractor. Each XOR gate receives one input from M and the other input from B, i.e. Bi. The map of the XOR gate is that if both the inputs of the XOR gate is the same, so the end product of the XOR gate will be zero and if both the inputs to the XOR gate are different, so the end product of the XOR gate will be 1.
When M = 0, the end product of XOR gate will be Bi ? 0 = Bi. Thus, the add-on map takes topographic point, i.e. the circuit performs A asset B ( A + B ) . When M = 1, the end product of XOR gate will be Bi ? 1 = Bi ‘ . Since it is the complement of B, minus map takes topographic point, i.e. A plus 1 ‘s complement of B which is the same as A subtraction B ( A – Bacillus ) .
Fig 9: Logic Diagram of a 4 – Bit Adder / Subtractor circuit
Every digit place consists of two operands and a carry. The operation of an adder is to add the two operands and the carry-in together. If the consequence is less than the base, this amount is outputted with a carry-out of 0. 0therwise the base is subtracted from the sum of the two operands and the carry-in and this amount is outputted with a carry-out.
3.3.2 BCD – 7 section show decipherer
Here, the end product of the Binary analogue adder forms the input for this BCD – 7 section decipherer to expose the random figure from 1 – 6.
The inputs A – Calciferol for the BCD ( Binary Coded Decimal ) show driver are connected from the end products of the parallel adder. The show driver consists of a web of logic Gatess to do its end products a – g become high or low. This lights the needed sections a – g of a 7-segment show as shown in the figure. Normally, a resistance is required in series with each section to protect the LEDs, 330 or 270 is a suited value for many shows with a 4.5V to 6V supply. But for this undertaking, merely one 270 resistance is used which is connected between 3 ( expose trial ) and 8 ( land ) pins of the integrated circuit.
Fig 10: Display driver with 7 – section show
There are two types of 7-segment shows:
Common Cathode ( CC or SC ) : This show consists of all the cathodes connected together. These need a show driver with end products which become high to light each section, i.e. they are illuminated with high electromotive forces. For illustration the IC – 4511. Here, there is a connexion between the common cathode to 0V. Intelligence community 4511 is designed to drive a common cathode show and therefore would non work with the common anode show.
Common Anode ( CA or SA ) : This show consists of all the LED anodes connected together. These need a show driver with end products which become low to light each section, i.e. they are illuminated by linking with low electromotive forces. For illustration, IC – 7447 ( BCD – 7 section decipherer ) which is the IC used for this undertaking. Here, there is a connexion of a resistance in series between the common anode to +Vs.
The 7447 bit is used to drive 7 section show. The input to the 7447 is a binary figure DCBA where D is 8s ( 1000 ) , C is 4s ( 0100 ) , B is 2s ( 0010 ) and A is 1s ( 0001 ) . The IC – 7447 show is intended for BCD ( binary coded decimal ) which has input values from DCBA = 0000 ( 0 ) to DCBA = 1001 ( 9 ) ( i.e. 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001 in binary ) . Inputs from 10 to 15 ( 1010, 1011, 1100, 1101, 1110, 1111 in double star ) will illume uneven show sections.
The undermentioned maps can be performed on the IC – 7447:
This IC has an unfastened aggregator outputs a – g, which can drop up to 40mA.
A lamp trial can be performed on the IC to look into if all the sections are in working status. This is done by maintaining the portion of the IC low. At this point of clip, all the show sections should illume ( demoing figure 8 ) .
There is another map which is the Blanking Input ( ) . If the space input is low, so the show will be clean when the count input is zero ( 0000 ) . This can be used to blank taking nothings when there are several show figures driven by a concatenation of counters. The clean end product can be achieved by linking the clean input of the following show down the concatenation ( i.e. the following most important figure ) .
Besides, a map stands for Ripple Blanking Input. When is low and DCBA = 0000, the show is clean otherwise the figure is displayed on the show. This is used to take taking nothings from a figure. For illustration, displays 89 alternatively of 089. If more than one show has to be used, a connexion of ( Ripple Blanking Output ) from most important 7447 to the of the following 7447 has to be done.
If a connexion between of the least important 7447 to 5V is done, the show will turn off when the figure is 0.
This circuit can besides be controlled by a PLC ( Programmable Logic Circuit ) , if the inputs to the BCD ( Binary Coded Decimal ) come from the 4 end product spots of the PLC end product card.
This chapter lists the accomplishments and developments of the undertaking
The followers has been achieved in this undertaking:
Successful design and simulation of random figure coevals circuit along with the dies display – Block Diagram of the Digital Dice game, circuit diagram for the show of random Numberss from 1 – 6 on the 7 – section show.
Successful assembly of wires, binary rippling counter ( IC – 7493 ) , binary analogue adder ( IC – 7483 ) , BCD – 7 Segment show decipherer ( IC – 7447 ) .
The development of this undertaking is as follows.
The digital die game is presently being assembled, and station assembly, it will be used as a game to be played between two players..
Staying circuit diagrams with more item about the staying parts of the block diagram will be designed.