We have decided to design a one-step Flash converter. As shown in the schematic below, in this type of ADC the input signal is compared to the 2n nodes of resistors.
At the output of the comparators, the sampled input value can be read in the thermometer-code. At the beginning of this project, we were novices in circuit designing. Due to a large number of resistors and comparators (2N? 1 comparator required), we have chosen to design a 3-bit Flash A/D Converter (7 comparators required).
We were interested in this type of structure because there are lots of different components to design: Resistors, logic gates, operational amplifiers. In this report, we will deal with all these functions, beginning with the design of a comparator.
Next, we will analyze how we can divide a reference voltage into comparison steps. It is required to decode the thermometer code into binary code. And to conclude, we have decided to add a system to remove the bubble errors of this ADC.
We will use the operational amplifiers as a comparator. Let us try to build a very simple comparator: This comparator is very easy to design, but the test results are not satisfactory. We have simulated this circuit with two inputs: a sinus with an offset of 0. 5V and a continuous signal Vseuil=0. V. The results of the test are just above. It is very easy to observe the inefficiency of this comparison system. It is impossible to reach 0, and the rise time is obviously too long. That is why, we had decided to search an other comparator, which would be more efficient.
We have decided to do another comparator, more complex. This comparator introduces a setup of rising time with V-bias.
N1 N2 N3 N4 N5 N6 P1 P2 P3 P4 P5 VDD VDD VDD VDD VDD VIN+ VIN- VOUT Vbias V-bias must be included in VTN of transistor and Vdd/2.
VTN provide by transistor characteristics and is approximate 0. 2V for optimal functioning. For our system, V-bias must be included in 0. 2V and 0. 5V. We choose V-bias=0. 3V. , we see a long rise time for V-out and impossible to reach the Vdd. This sample is rejected. With V-bias=0. 9V, Vout is always with long rise time but the signal is more efficient for reach Vdd. This sample is always rejected. Vout is faster and the crests value is reached.
This comparator with sample 3 is more elaborate but especially more efficient. The 0 and 1 levels are easily reached and the rise time is ten times faster.
III- Voltage Divider
In the first part, we will analyze a voltage divider realized with nMOS connected as diodes. The schematic used is this one: To obtain our voltage divider, we have to choose the same equivalent resistor for both nMOS. But the equivalent resistance of an nMOS is commensurate with W/L. Dividing by 2 the voltage requires resizing the nMOS because the polarization of the 2 nMOS is not the same.
This type of circuits uses less area than circuit realized with strips of polysilicon but is not so accurate. With lot of resizing on W and L, we finally reached Vref = 0. 502*Vdd. This method can’t be used with more than 3 CMOS connected as a diode because of the substrate voltage VTN = 0. 2V. In our application, we want to divide by 8 the input voltage (1 Volt). So much, this is very impossible to modify each transistor to generate the same quantum. That is why it will be impossible to use this method to obtain a voltage divider. Let us try with a classical circuit: 8 resistors serially connected.
Each one had the same value. We also reach to divide by 8 the input voltage with fine accuracy.
We use the circuit opposite on left as add the same quantum as VPE. The value of resistors that we use is the same and R1=R2=R…=R=1Kohms. The simulation is opposite on right. The values we obtain are correct but the value of a0 is too small. a0 could be superior to 0. 2V, the VTN value of comparator for powered correctly the transistor. The simulation of the out of comparator with this divider stage gives us: The out is very bad.
The signal does not even achieve Vdd/2. We thus decided to modify the quantum of the voltage divider. We decided to put the first and last quantum as 0. 2V, the other as 0. 1V for VPE=1V. We choose R1=R8=2Kohms and R2=R3=R4=R5=R6=R7=1Kohms. We obtain the following results: The simulation of the out of comparator gives us: The out is as good as previously. Vdd is reached and the next stage can interpret the signal. R4 R3 R2 R1 R8 R7 R6 R5 Vcc a0 a1 a2 a3 a4 a5 a6
IV- Bubble Errors
Incorrect comparator output signals caused by comparator metastability, noise, etc. lead to faulty thermometer-code representation. This phenomenon, a 1 appearing between zeros or a 0 appearing between ones close to the transition between 0 and 1 is called bubble error. Most of this bubble error can be removed by using three-input NAND gates (see fig. below). A one appearing between two 0 caused no mistakes at the output stage. Let us apply this method to our system: the outputs of the comparators switched to 0 when the input voltage increase. A corresponding to the LSB and G to the MSB.
Yet, we have to design an inverter and a three-input NAND gate. Let’s begin with the inverter. The principle is easy. A nMOS and a pMOS connected together with a common gate. Now, we will design a 3-input NAND gate. The circuit is composed of 3 nMOS and 3 pMOS. The results meet the requirements. The output signal had a very short rise time. The 0 and the 1 are perfectly reached. Yet, we connect the input and simulate. At the output of the NAND gates, we observe an inverted step while the input signal is in the interval.
In this case, we will use two NAND gates and an OR gate in order to realize an equivalent to a 4-input NAND gate. The result of the combination of 2 NAND and an OR gate is the same as a 4-input NAND gate. And the simulation gives us this result: Without error, the output is correct. The word (S2-S1-S0) is increasing while Vin increases. The outputs of the comparators switched to 0 as soon as VIN becomes higher than the comparison voltage.
But the aim of this circuit is to remove bubble-errors too. We will simulate a defect comparator (Ve on Simulation, which never switched to 0). We observe that the word (S2-S1-S0) contained an error exclusively when Vin is between Ve and Vf. Without error, the maximal error between the input signal and the output is Quantum/2. When an error occurred, we reach a maximal error of (3*Quantum) /2.
V- Final Design andTests
All the different components of our circuit are designed and tested. We have to assemble all of these and to test.
The final design is this one: The basic function of our circuit is accomplished. While Vin is increasing, the word (S2-S1- S0) counts up. There are some glitches during the transitions. Slightly different delays lead to a momentarily erroneous output value. A way to suppress glitches is adding a Sample and Hold circuit at the output
Cite this The Design of One-step Flash Converter
The Design of One-step Flash Converter. (2018, Jul 26). Retrieved from https://graduateway.com/3bit-adc/