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1508 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 8, AUGUST 2005 Design Procedure for Two-Stage CMOS Opamp With Flexible Noise-Power Balancing Scheme Jirayuth Mahattanakul, Member, IEEE, and Jamorn Chutichatuporn Abstract—This paper presents a basic two-stage CMOS opamp design procedure that provides the circuit designer with a means to strike a balance between two important characteristics in electronic circuit design, namely noise performance and power consumption.

It is shown in this paper that, unlike the previously reported design procedures, the proposed design step allows opamp designers to trade between noise performance and power consumption with greater ? exibility.

In order to verify the viability of the proposed design step, SPICE simulation results of the opamp designed by the proposed procedure, under a variety of temperature and process conditions, are given. Index Terms—CMOS analog integrated circuits, frequency compensation, operational ampli? er, poles and zeroes. Fig. 1. Basic two-stage CMOS opamp.

I. INTRODUCTION MOS opamps are ubiquitous integral parts in various analog and mixed-signal circuits and systems.

The two-stage CMOS opamp shown in Fig. 1 is widely used because of its simple structure and robustness. In designing an opamp, numerous electrical characteristics, e. g. , gain-bandwidth, slew rate, common-mode range, output swing, offset, all have to be taken into consideration. Furthermore, since opamps are designed to be operated with negative-feedback connection, frequency compensation is necessary for closed-loop stability.

Unfortunately, in order to achieve the required degree of stability, generally indicated by phase margin, other performance parameters are usually compromised. As a result, designing an opamp that meets all speci? cations needs a good compensation strategy and design methodology. The simplest frequency compensation technique employs the across Miller effect by connecting a compensation capacitor the high-gain stage. A design procedure for this type of opamp can be found in [1]. However, due to an unintentional feed-forward path through the Miller capacitor, a right-half-plane (RHP) zero is also created and the phase argin is degraded. Such a zero, however, can be removed if a proper nullifying resistor is inserted in series with the Miller capacitor [1]–[5]. A design procedure for the zero-nulli? cation opamp can be found in [2]. is an imIt will be shown in Section III that the value of portant factor when determining noise and power, e. g. , by decreasing , power consumption can be reduced but at the expense of noise performance. Unfortunately, one of the necesManuscript received February 13, 2003; revised June 22, 2004 and December 13, 2004. This paper was recommended by Associate Editor P. Wambacq.

J. Mahattanakul is with the Mahanakorn University of Technology, Bangkok 10530, Thailand (e-mail:[email protected] ac. th). J. Chutichatuporn is with the RGY Hydraulic Company, Cholburi 20170, Thailand (e-mail: [email protected] com). Digital Object Identi? er 10. 1109/TCSI. 2005. 851395 C sary imposing conditions of the design procedure in [2] is being much larger than the parasitic capacitance associated with the input node of the high-gain stage. This condition thus reduces one important degree-of-freedom in analog circuit design, namely the tradeoff between noise and power consumption.

In this work, it has been shown that by employing such a technique, the value of the compensation capacitor, , can be made much smaller than when employing other techniques. As provides such, the ? exibility of choosing a wider range of the designer with a greater degree of freedom to optimize the opamp in terms of noise and power. II. BASIC OPAMP EQUATIONS For simplicity, both the mobility reduction due to the normal ? eld and the velocity saturation effect associated with MOS devices will be neglected. The following MOSFET, strong-inversion, square-law equations: (1) (2) (3) for nMOS and where for PMOS, will be used throughout the paper.

Strong inversion greater than approximately 200 typically requires values of to 250 mV for bulk MOSFET’s at room temperature. The equations for determining various opamp characteristics can be shown as follows [1]–[4]. A. Gain and Bandwidth According to the equivalent circuit shown in Fig. 2, under , and typical conditions , the small-signal transfer function of the CMOS 1057-7122/$20. 00 © 2005 IEEE Authorized licensed use limited to: AMITY University. Downloaded on November 16, 2009 at 05:58 from IEEE Xplore. Restrictions apply. MAHATTANAKUL AND CHUTICHATUPORN: DESIGN PROCEDURE FOR TWO-STAGE CMOS OPAMP 509 D. Internal Slew Rate The slew rate associated with can be found to be (12) Fig. 2. r ==r Small-signal equivalent circuit of CMOS opamp in Fig. 1 where R and R r =r . = = E. External Slew Rate The slew rate associated with can be found to be (13) Combining (12) and (13), we obtain (14) Combining (3), (6), (12), and yields (15) opamp in Fig. 1 can be shown as (4), shown at the bottom of the is the opamp dc gain. page, where The opamp’s dominant pole frequency and unity-gain bandwidth, also commonly known as gain-bandwidth, can be found to be (5) and (6) respectively.

It can also be shown that for, mated as F. Offset Voltage Minimization Systematic offset is caused by current imbalance in the output and , when there is no input voltage. stage, i. e. , between and is Under such a condition, thus forced to be equal to . Since and , we then have , which implies . that and , we have Now considering . As a result, the current imbalance in the output stage can be minimized by the following condition: (16) which can be used to minimize the offset voltage. G. Input-Referred Thermal Noise Spectral Density , (4) can be approxi- (7) B. Output Swing By de? ning i. . , as the opamp headroom voltage at output, and according to Fig. 1, it is easy to show that (8) (9) The input-referred thermal noise spectral density of the two-stage opamp in Fig. 1 can be shown to be (17) C. Common-Mode Range If we de? ne as the opamp head room voltage of the input common-mode range, i. e. , and according to Fig. 1, it can be shown that (10) (11) From (3), (10), and (12), we obtain (18) Substitute (6) and the above equation into (17) yields (19) (4) Authorized licensed use limited to: AMITY University. Downloaded on November 16, 2009 at 05:58 from IEEE Xplore.

Restrictions apply. 1510 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 8, AUGUST 2005 Fig. 3. Noise-spectral density versus power consumption. III. NOISE VERSUS POWER TRADEOFF In this section, we will consider in detail the noise and power tradeoff encountered in the opamp design. The quiescent power consumption of the two-stage opamp shown in Fig. 1 can be found to be (20) where above equation gives . Substitute (12) and (14) into the (21) According to (19) and (21), Fig. 3 illustrates con? ict between noise and power consumption in two-stage CMOS opamp design.

For example, by decreasing , power consumption can be reduced at the expense of the noise performance. Consequently, would the compensation scheme that allows a wider range of provide a higher degree of freedom in noise and power tradeoff. It should be highlighted that one of the necessary conditions . This condiof the design procedure in [2] is that tion would clearly reduce the degree of freedom in the tradeoff between noise and power consumption. IV. COMPENSATION SCHEME AND PHASE MARGIN CONTROL It can be shown that Fig. 4(a) is a circuit that corresponds to the transfer function (7), i. . , it is a small-signal circuit of the . opamp in Fig. 1 in the higher frequency range where Under the condition (22) it can be shown that (see Appendix A) the circuit of Fig. 4(a) and are can be transformed into that of Fig. 4(b) where effectively connected in parallel. It is thus easy to show that (23) is the unity-gain frequency of an opamp. where Equation (23) indicates that the condition of (22) results in a system with only one nondominant pole (24) and no ? nite zero. Fig. 4. High-frequency small-signal equivalent circuit of CMOS opamp in Fig. . Alternatively, the above compensation scheme can be viewed as a mean to locate the extra zero and pole of the system at exactly the same location. This can be explained as follows. By substituting the condition (22) into (7), which is a transfer func, the zero of the transfer function tion of the opamp for can be easily identi? ed as (25) and the nondominant poles are the roots of a polynomial (26) which are exactly (27) (28) It can be seen that the condition (22) results in the cancellation and . Also, is identical to the pole expressed in (24). f It should be pointed out here that, unlike the analysis presented elsewhere [1]–[5], the pole location shown in (28) are the exact solutions of the second-order polynomial and no approximation is involved. The phase margin of an opamp with one nondominant pole, considered for 100% feedback, can be shown to be (29) From (24) and (29), we obtain (30) Authorized licensed use limited to: AMITY University. Downloaded on November 16, 2009 at 05:58 from IEEE Xplore. Restrictions apply. MAHATTANAKUL AND CHUTICHATUPORN: DESIGN PROCEDURE FOR TWO-STAGE CMOS OPAMP 1511

Step 6) Calculate (2) yields from (6) and use the result with to calculate from (38) Step 7) Calculate from (11) and (15) and substitute the result into (1) gives Fig. 5. Two-stage CMOS opamp. (39) where (31) is a transition frequency of M6 and Combining (8), (30) and (31), we ? nd that [3]. Step 8) Calculate from the basic relation in conjunction with (12) and (13) yields (40) (32) is a necessary condition in our opamp design. It is important to note that as opposed to the method in [2] is not necessary for the compensation the condition , it scheme presented in this section.

Furthermore, for can be shown that Step 9) Calculate from (16) (41) Step 10) Calculate from (22) and use (3), (14) and the triode equation which indicates that, compared to [2], the proposed method allows the use of smaller . V. DESIGN PROCEDURE A design step for two-stage opamp (Fig. 5) can be constructed as follows. Step 1) From (19), we have (33) Step 2) Calculate from (14) (34) Step 3) Using (32) to calculate (35) Step 4) Calculate late from (8) and use the result to calcufrom (1) yields (36) Step 5) Calculate from (12) (37) where gives to calculate 42) The design steps outlined above can be summarized as shown in Table I. VI. SIMULATION RESULTS For the process parameters shown in Table II and opamp speci? cation shown in Table III, design parameters of opamp in Fig. 4 are obtained from our proposed procedure (Table I) and the procedure proposed in [2]. These parameters are shown and 0. 5 pF. HSPICE simulation results in Table IV for of the designed opamps are shown in Tables V and VI. pF, the It can be observed from Table V that for characteristics of both opamps meet all the speci? cations.

HowpF, while the characteristics of the ever in the case for opamp designed by the proposed procedure pass all the speci? cations, such is not the case for those of the opamp designed by the procedure in [2], notably the phase margin. It should be noted that, as expected, by using the same value of , there is no improvement in terms of noise performance Authorized licensed use limited to: AMITY University. Downloaded on November 16, 2009 at 05:58 from IEEE Xplore. Restrictions apply. 1512 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 2, NO. 8, AUGUST 2005 TABLE I OPAMP DESIGN STEP TABLE IV DESIGN PARAMETERS TABLE V SIMULATION RESULTS FOR C = 2 5 pF : TABLE VI SIMULATION RESULTS FOR C = 0:5 pF TABLE II PROCESS PARAMETERS (0. 5 MICRON HP’S CMOS14TB) [6] TABLE III SPECIFICATION OF CMOS OPAMP vides the designer with a higher degree of freedom to optimize the opamp in terms of noise and power. Fig. 6 shows a two-stage opamp with robust bias part [4]. and For , it can be shown that (43) If is chosen to be , we have (44) when using the method proposed.

However, by using the procan be made much smaller than posed method, the value of the method in [2] without affecting the phase margin. This proAuthorized licensed use limited to: AMITY University. Downloaded on November 16, 2009 at 05:58 from IEEE Xplore. Restrictions apply. (45) MAHATTANAKUL AND CHUTICHATUPORN: DESIGN PROCEDURE FOR TWO-STAGE CMOS OPAMP 1513 Fig. 6. Two-stage CMOS opamp with robust bias circuit. Fig. 7. Network transformation. TABLE VII DESIGN PARAMETERS OF OPAMP IN FIG. 6 VII. CONCLUSION The design procedure for two-stage CMOS opamp has been presented.

Simulation results con? rm that the proposed design step is more ? exible than the one proposed in [2]. This is due is not required in the to the fact that condition proposed step. The Proposed procedure thus provides circuit designers with a higher degree-of-freedom to optimize their opamps in terms of noise performance and power consumption. Furthermore it has been shown that with proper biasing circuit, the opamp designed from the proposed procedure is tolerant to various process and temperature variation.

However, since the pole/zero cancellation scheme seems to be more susceptible to variations than other compensation techniques, further investigation might be necessary to ensure suitability of the proposed procedure for particular applications. It should also be pointed out that although this paper does not concern power-supply noise contribution, rejection ratio, mismatched offset and these quantities can be improved by increasing the device area ) while maintaining the ratio. (i. e. , increasing APPENDIX NETWORK TRANSFORMATION For a network shown in Fig. 7(a), it can be shown that if (A1)

TABLE VIII PROCESS AND TEMPERATURE VARIATION TABLE IX SIMULATION RESULTS FOR PROCESS AND TEMPERATURE VARIATION and , such a network can be where transformed into that shown in Fig. 7(b) where the voltage is found to be (A2) Hence, under the condition (A1), the current ? owing through in Fig. 7(a) is (A3) Design parameters of the opamp designed by our proposed design step, complete with robust bias part, is shown in Table VII. HSPICE simulation results of such an opamp under a variety of process conditions and parameters (Table VIII) are shown in Table IX where its robustness is evident.

Substituting (A1) into (A3) yields (A4) Authorized licensed use limited to: AMITY University. Downloaded on November 16, 2009 at 05:58 from IEEE Xplore. Restrictions apply. 1514 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 8, AUGUST 2005 According to (A4), it is apparent that under the condition of (A1), the network shown in Fig. 7(a) can be transformed into that shown in Fig. 7(c) where (A5) ACKNOWLEDGMENT The authors would like to thank Mr. K. Grimshaw, Shrewsbury International School, Bangkok, Thailand, for his special help.

REFERENCES [1] P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design. New York: Oxford Univ. Press, 2002. [2] G. Palmisano, G. Palumbo, and S. Pennisi, “Design procedure for two-stage CMOS transconductance operational ampli? ers: A tutorial,” in Analog Integrated Circuits and Signal Processing. Norwell, MA: Kluwer, 2001, vol. 27, pp. 179–189. [3] P. Gray, P. Hurst, S. Lewis, and R. Meyer, Analysis and Design of Analog Integrated Circuits. New York: Wiley, 2001. [4] D. A. Johns and K. Martin, Analog Integrated Circuit Design. New York: Wiley, 1997. 5] G. Palmisano and G. Palumbo, “An optimized compensation strategy for two-stage CMOS opampS,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl. , no. 3, pp. 178–182, Mar. 1995. [6] R. J. Baker, H. W. Li, and D. E. Boyce, CMOS Circuit Design, Layout, and Simulation. New York: Wiley Interscience, 1998. Jirayuth Mahattanakul (S’91–M’98) was born in Bangkok, Thailand, in 1968. He received the B. Eng. degree from King Mongkut’s Institute of Technology, Bangkok, Thailand, the M. S. degree from Florida Institute of Technology, Melbourne, and the Ph. D. egree from Imperial College London, London, U. K. , in 1990, 1992, and 1998, respectively, all in electrical engineering. From 1992 to 1994, he was with TelecomAsia, Bangkok, Thailand, in the Network Planning and Engineering Division. In 1994, he joined Mahanakorn University of Technology, Bangkok, Thailand, where he is currently a Dean of Graduate School and an Associate Professor of Electronic Engineering. Dr. Mahattanakul was a member of the Executive Committee of the Engineering Institute of Thailand and is a committee of the IEEE Circuits and Systems Chapter—Thailand Section.

Jamorn Chutichatuporn was born in Cholburi, Thailand, in 1977. He received the B. Eng. and the M. Eng. degrees in electronic engineering from Mahanakorn University of Technology in 2000 and 2002, respectively. From 2003 to 2004, he was with Delta Electronics (Thailand) Public Company Limited, Samutprakarn, Thailand, in the R&D Division. Since 2004, he joined RGY Hydraulic Company, Cholburi, Thailand, where he is currently a General Manager. Authorized licensed use limited to: AMITY University. Downloaded on November 16, 2009 at 05:58 from IEEE Xplore. Restrictions apply.

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