CMOS and Design Procedure for Two-Stage CMOS Opamp

Abstract

This paper presents a basic two-stage CMOS opamp design procedure that provides the circuit designer with a means to strike a balance between two important characteristics in electronic circuit design, namely noise performance and power consumption.

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It is shown in this paper that, unlike the previously reported design procedures, the proposed design step allows opamp designers to trade between noise performance and power consumption with greater ? exibility. In order to verify the viability of the proposed design step, SPICE simulation results of the opamp designed by the proposed procedure, under a variety of temperature and process conditions, are given. Index Terms—CMOS analog integrated circuits, frequency compensation, operational ampli? er, poles and zeroes. Fig. 1. Basic two-stage CMOS opamp.

INTRODUCTION

MOS opamps are ubiquitous integral parts in various analog and mixed-signal circuits and systems. The two-stage CMOS opamp shown in Fig. 1 is widely used because of its simple structure and robustness. In designing an opamp, numerous electrical characteristics, e. g. , gain-bandwidth, slew rate, common-mode range, output swing, offset, all have to be taken into consideration. Furthermore, since opamps are designed to be operated with negative-feedback connection, frequency compensation is necessary for closed-loop stability.

Unfortunately, in order to achieve the required degree of stability, generally indicated by phase margin, other performance parameters are usually compromised. As a result, designing an opamp that meets all speci? cations needs a good compensation strategy and design methodology. The simplest frequency compensation technique employs the across Miller effect by connecting a compensation capacitor the high-gain stage. A design procedure for this type of opamp can be found in.

However, due to an unintentional feed-forward path through the Miller capacitor, a right-half-plane (RHP) zero is also created and the phase argin is degraded. Such a zero, however, can be removed if a proper nullifying resistor is inserted in series with the Miller capacitor . A design procedure for the zero-nulli cation opamp can be found in  is an imIt will be shown in Section III that the value of portant factor when determining noise and power, e. g. , by decreasing , power consumption can be reduced but at the expense of noise performance. C sary imposing conditions of the design procedure in is being much larger than the parasitic capacitance associated with the input node of the high-gain stage. This condition thus reduces one important degree-of-freedom in analog circuit design, namely the tradeoff between noise and power consumption.

In this work, it has been shown that by employing such a technique, the value of the compensation capacitor, , can be made much smaller than when employing other techniques. As provides such, the  exibility of choosing a wider range of the designer with a greater degree of freedom to optimize the opamp in terms of noise and power.

BASIC OPAMP EQUATIONS

For simplicity, both the mobility reduction due to the normal ? eld and the velocity saturation effect associated with MOS devices will be neglected. The following MOSFET, strong-inversion, square-law equations:  for nMOS and where for PMOS, will be used throughout the paper.

Strong inversion greater than approximately 200 typically requires values of to 250 mV for bulk MOSFET’s at room temperature. The equations for determining various opamp characteristics can be shown as follows . The slew rate associated with can be found to be  Combining  and , we obtain Combining and yields, shown at the bottom of the is the opamp dc gain. page, where The opamp’s dominant pole frequency and unity-gain bandwidth, also commonly known as gain-bandwidth, can be found to be and respectively.

It can also be shown that for, mated as F. Offset Voltage Minimization Systematic offset is caused by current imbalance in the output and , when there is no input voltage. stage, i. e. , between and is Under such a condition, thus forced to be equal to . Since and , we then have , which implies . that and , we have Now considering . As a result, the current imbalance in the output stage can be minimized by the following condition: which can be used to minimize the offset voltage. Input-Referred Thermal Noise Spectral Density.

NOISE VERSUS POWER TRADEOFF

In this section, we will consider in detail the noise and power tradeoff encountered in the opamp design.  For example, by decreasing , power consumption can be reduced at the expense of the noise performanc. Consequently, would the compensation scheme that allows a wider range of provide a higher degree of freedom in noise and power tradeoff. It should be highlighted that one of the necessary conditions . This condiof the design procedure in  is that tion would clearly reduce the degree of freedom in the tradeoff between noise and power consumption.

REFERENCES

  1. P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design. New York: Oxford Univ. Press, 2002.
  2. G. Palmisano, G. Palumbo, and S. Pennisi, “Design procedure for two-stage CMOS transconductance operational ampli? ers: A tutorial,” in Analog Integrated Circuits and Signal Processing. Norwell, MA: Kluwer, 2001, vol. 27, pp. 179–189.
  3. P. Gray, P. Hurst, S. Lewis, and R. Meyer, Analysis and Design of Analog Integrated Circuits. New York: Wiley, 2001.
  4. D. A. Johns and K. Martin, Analog Integrated Circuit Design. New York: Wiley, 1997.
  5. G. Palmisano and G. Palumbo, “An optimized compensation strategy for two-stage CMOS opampS,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl. , no. 3, pp. 178–182, Mar. 1995.
  6. R. J. Baker, H. W. Li, and D. E. Boyce, CMOS Circuit Design, Layout, and Simulation. New York: Wiley Interscience, 1998.

 

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CMOS and Design Procedure for Two-Stage CMOS Opamp. (2018, Mar 08). Retrieved from https://graduateway.com/cmos-and-design-procedure-for-two-stage-cmos-opamp/